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A high-speed, asynchronous, digital multiplier

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2 Author(s)

The digital multiplication of two numbers of any sign by the successive addition of partial products is critically examined for the purpose of reducing the time of computation. The theory of Booth's method is reviewed and extended to show its validity for use with numbers of any radix. Multiple digit multiplication algorithms can then be derived and the quaternary algorithm for the multiplication of binary numbers two digits at a time is presented. Using this algorithm, computed results for numbers of varying size confirm that the carry propagation time, averaged over the whole multiplication, is very nearly one-half that obtained by either Booth's or Robertson's method. A further significant decrease in computing time can be achieved by using asynchronously-operated circuits and a three-bit multiplier, using Booth's algorithm, was constructed, using R-T micrologic elements, to check stability; a maximum multiplication time of 650 ns was achieved together with wide stability margins. A design for a multiplier using the faster quaternary algorithm is presented and it is envisaged that by using high-speed logical elements in its implementation a multiplication time of less than 1 fis should be achieved for 16-bit numbers.

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Radio and Electronic Engineer  (Volume:36 ,  Issue: 6 )