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Asynchronous sequential logic using NOR/NAND integrated circuits is extensively used in fast digital systems. The standard design procedure results in a set of excitation equations for the secondary variables, which must be examined (and corrected) for static logical hazards prior to implementation. A modified design technique is postulated which allows sequential circuits to be implemented directly in terms of d.c. set/reset bistables (i.e. cross-coupled NOR/NAND elements). It is shown that the use of d.c. bistables in this manner prevents the occurrence of static hazards, thus obviating hazard correction. Additional advantages are that the-circuits evolved use fewer modules than conventionally designed logic, and exhibit a simpler logical structure. Detailed designs (both methods are used for comparison) for an asynchronous Gray-code counter, employing TTL logic, are described.