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Compact modeling of vertical ESD protection NPN transistors for RF circuits

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2 Author(s)
Sopan Joshi ; Department of Electrical & Computer Engineering · University of Illinois at Urbana-Champaign, 1308 W. Main St., 61801, USA ; Elyse Rosenbaum

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.

Published in:

2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.

Date of Conference:

6-10 Oct. 2002