Switching dynamics and current flow homogeneity under very fast TLP (vf-TLP) stress is investigated in smart power and CMOS technology ESD protection devices by means of optical transient interferometric mapping (TIM) techniques with sub-nanosecond time resolution. Comparison between the device behavior under vf- and conventional TLP stress is discussed. The sub-ns time resolution enables a detailed insight into the triggering behavior of protection elements.
Published in:
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Date of Conference: 6-10 Oct. 2002