By Topic

The fast packet ring switch: a high-performance efficient architecture with multicast capability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Rahnema, M. ; Aeronaut. Radio, Annapolis, MD, USA

An architecture is presented for the packet switching of integrated traffic. It is based on the asynchronous routing of packets of varying size through regularly recurring dedicated time slots provided by a simple slotted-ring system. The architecture implements the distributed buffering and processing of packets, is data driven, and is designed to exploit fully the limited bandwidth of the ring system. Thus, switch modules of reasonable size and throughput are made feasible. The switch modules can be easily interconnected to achieve sufficient throughput for networking of services such as voice, data, image, and videoconferencing. The architecture provides a simple modular switching structure which does not suffer from the topological complexities and bottlenecks of those that use the staged Banyan-type networks for the switching of packets. Quasicircuit-switching can easily be achieved through selected ports with a peak bit-rate bandwidth allocation strategy in the switch control. Multicasting in particular is made simple and efficient in the current architecture. Moreover, it provides for the selective queueing of packets in the transmit ports

Published in:

Communications, IEEE Transactions on  (Volume:38 ,  Issue: 4 )