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The impact of self-heating in strained-Si MOSFETs on the switching characteristics of a complementary-metal-oxide-semiconductor (CMOS) inverter and the voltage gain of a push-pull inverting amplifier is assessed by technology-computer-aided-design (TCAD) simulations. Strained-Si nMOSFETs on 4-mum- and 425-nm-thick silicon-germanium strain-relaxed buffers (SiGe SRB) are cofabricated with silicon control nMOSFETs and used to calibrate the TCAD models. The measured data show a 50% reduction in thermal resistance from 30.5 to 16.6 K middot mW-1 as the thickness of the SiGe SRB is scaled from 4 mum to 425 nm. Using the calibrated models, electrothermal simulations of CMOS inverters are performed by accounting for heat generation from carrier flow using the fully coupled energy-balance equations for electrons and holes. The results of the TCAD simulations show that the inverter voltage gain can be maximized by balancing the opposing effects of drain induced barrier lowering (DIBL) and self-heating i.e. DIBL increases the drain conductance whereas self-heating reduces the drain conductance. DIBL is shown to limit the simulated voltage gain of the Si control inverter, whereas self-heating in the strained-Si nMOSFET on the 4-mum-thick SiGe SRB is shown to cause anomalous operation in the simulated inverter characteristics. The inverter voltage transfer characteristics simulated with the strained-Si nMOSFETs on the 425-nm SiGe SRB exhibited the highest voltage gain. The thickness of the SiGe SRB is presented as a design parameter for optimizing the analog performance of strained-Si MOSFETs.