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High-level timing analysis using constraint logic programming and interval arithmetic

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2 Author(s)
Girodias, P. ; Dept. d''Inf. et de Recherche Oper., Montreal Univ., Que., Canada ; Cerny, E.

This paper addresses the specific problem of true (functional) delay estimation during high-level design. We present a method for modelling and verifying high-level timing specification using CLP (BNR), a constraint logic programming language augmented with relational interval arithmetic

Published in:

Electrical and Computer Engineering, 1995. Canadian Conference on  (Volume:2 )

Date of Conference:

5-8 Sep 1995