Cart (Loading....) | Create Account
Close category search window

A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Sasaki, M. ; Hiroshima Univ., Higashi-Hiroshima, Japan

The present paper introduces a resonant clock generation and distribution scheme that uses uniform amplitude and uniform phase standing wave oscillators in order to distribute a high-frequency clock signal with low skew, low jitter, and low power. A suitable distributed resonator for a global clock distribution that is inductively loaded transmission line generating a uniform amplitude and uniform phase standing wave is realized through detailed analysis of a standing wave on a loaded transmission line. A test chip is fabricated using 0.18-mum 6 M CMOS technology, and a cascaded distribution network is implemented for a global clock distribution with a space-filling curve. Furthermore, distributed local LC tanks are implemented as local resonant clock networks, which are composed of parasitic capacitors and small spiral inductors. The distributed local LC tanks are driven by a fine clock distributed with cascaded standing-wave oscillators and reduce the primary power in the clock distribution, which is dissipated as dynamic power in the parasitic capacitance of latches and/or flip flops. The measurement results reveal that, at 9.4 GHz, the peak-to-peak jitter is 5.2 ps and the clock skew is 0.8 ps, and the global and local distributions dissipated only 17% and 23% of CV2 f power, respectively.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 10 )

Date of Publication:

Oct. 2009

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.