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An efficient stream memory architecture for heterogeneous multicore processor

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6 Author(s)
Rangyu Deng ; School of Computer Science, National University of Defense Technology, Changsha, Hunan, 410073, China ; Weixia Xu ; Qiang Dou ; Hongwei Zhou
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Heterogeneous multicore processor can integrate merits of different architecture, so it can achieve peak performance as high as processors with special architecture, while keeping as flexible as traditional general purpose processors at the same time. It is a challenge to design a memory sub-system for FT64-3, which is a heterogeneous multicore processor with 18 float function units. In this paper, parallel stream memory sub-system architecture for FT64-3 is presented, not only its design idea to improve memory level parallelism (MLP) is described, but also the experiments and results analysis for kernel algorithms are detailed. Test results show that our application-specific memory sub-system can improve system performance significantly. The performance of FT64-3 with 500 MHz is 2-3 orders of that of FT64-2 with the same frequency, and is close to that of Itanium2 with 1.6 GHz at less cost.

Published in:

Multimedia Computing and Systems, 2009. ICMCS '09. International Conference on

Date of Conference:

2-4 April 2009