Cart (Loading....) | Create Account
Close category search window
 

692-nW Advanced Encryption Standard (AES) on a 0.13- \mu m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Good, T. ; Dept. of Electr. & Electron. Eng., Univ. of Sheffield, Sheffield, UK ; Benaissa, M.

This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-μm CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 μm2 and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power-latency-area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 12 )

Date of Publication:

Dec. 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.