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Microarchitectural Online Testing for Failure Detection in Memory Order Buffers

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4 Author(s)
Carretero, J. ; Intel Barcelona Res. Center, Intel Labs. Barcelona-UPC, Barcelona, Spain ; Vera, X. ; Chaparro, P. ; Abella, J.

Technology scaling leads to burn-in phase out and higher postsilicon test complexity, which increases in-the-field failure rate due to both latent defects and actual errors, respectively. As a consequence, current reliability qualification methods will likely be infeasible. Microarchitecture knowledge of application runtime behavior offers a possibility to have low-cost continuous online testing techniques detect hard errors in the field. Whereas data can be protected with redundancy (like parity or ECC), there is a lack of mechanism for control logic. This paper proposes a microarchitectural approach for validating that the memory order buffer logic works correctly. Our design relies on a small cache-like structure that keeps track of the last store to each cached address. Each load is checked to have obtained the data from the youngest older producing store. We present three different implementations of this idea, offering different trade-offs for error coverage, performance overhead, and design complexity.

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Computers, IEEE Transactions on  (Volume:59 ,  Issue: 5 )