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Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch

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4 Author(s)
Pouria Bastani ; University of California Santa Barbara, Santa Barbara ; Nick Callegari ; Li-C Wang ; Magdy S. Abadir

For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features can be interpreted properly.

Published in:

IEEE Design & Test of Computers  (Volume:27 ,  Issue: 3 )