By Topic

Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features can be interpreted properly.

Published in:

Design & Test of Computers, IEEE  (Volume:27 ,  Issue: 3 )