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Robust On-chip Signaling by Staggered and Twisted Bundle

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2 Author(s)
Yu, H ; UCLA, Los Angeles ; He, L

Existing shield insertion for multiple signal nets may lead to non-uniformly distributed capacitive coupling-length and inductive returned-path, and hence introduces large delay and delay variation by crosstalk. This paper discusses the design and test of a twisted and staggered interconnect structure to reduce both inductive and capacitive crosstalk. A transmission line model is introduced and an automatic layout synthesis is presented. Moreover, the proposed design is fabricated with IBM 0.13um process and tested by an on-chip time-domain sampling circuit. As shown by measurement, our proposed design reduces delay by 25% and reduces delay variation by 25X compared to interconnects with traditional coplanar shields.

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Design & Test, IEEE  (Volume:PP ,  Issue: 99 )