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Trigger dynamics during a single ESD event and pulse-to-pulse variations in the trigger location are studied in ESD protection devices of a smart power technology. NPN bipolar transistors with and without a lateral shift in the collector buried layer are investigated. The homogeneity of the current flow along the device width is studied by means of a laser interferometric thermal mapping technique. The investigations are performed as a function of device type, pulse duration and stress magnitude. The trigger behavior is correlated with the time evolution of holding voltage, shape of the high current IV curves, and results of failure analysis. A model for thermally - driven current flow dynamics is proposed and the failure mechanism is explained in terms of the observed thermal behavior.