Skip to Main Content
Based on synthesizing most sorts of phase/frequency locking mechanisims respectively shown in different conventional all digital phase-locked loop (all DPLL) systems, a novel all DPLL, which is with higher performances on wideband frequency tracking and also possesses a balance mechanisim for improving system performance on noise reduction as well as shortening time for arriving at a synchronous state, is proposed. The system has a parameters adaptation enginery, which ensures the synchronization of the phase/frequency of the output signal with that of input when a wide range of variance in phase/frequency of input signal occurs. The system is designed by using Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) and implemented on a Field Programmable Gate Array (FPGA) chip. And the simulation and experimental results show that the system possesses good robustness property, for it will return to its stable state within 4 clock cycles if input signal gives a frequency jump from 400 KHz to 160 KHz. Besides, it also takes on excellent performance on noise reduction. In a word, the system is characteristic of its simple circuit structure, excellent adaptation and robustness properties, and it is prone to system integration and thus can be packed as an IP core for SoC applications.
Hybrid Intelligent Systems, 2009. HIS '09. Ninth International Conference on (Volume:3 )
Date of Conference: 12-14 Aug. 2009