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Simulation results of a multiple-instruction multiple-data-stream (m.i.m.d.) organisation are presented. The results deal with the behaviour of throughput performance with respect to variations in cache-memory parameters, number of processors and processing time, of a m.i.m.d. system in which a pipelined binary switch is used as the interconnection network. The results indicate the viability of systems utilising cache memories and pipelined switches which exhibit performance comparable to systems with crosspoint switches. This aspect is attractive, since it is likely that m.i.m.d. systems with pipelined binary switches can be implemented at a lower cost than those with crosspoint switches.