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Performance analysis of nonblocking multi-plane ATM switches with input/output buffers and priorities

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3 Author(s)
Wu, J.-L.C. ; Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan ; Li-Der Chou ; Hung-Fu Su

The performance of an internally nonblocking multi-plane ATM switch with common input/output buffers is analyzed in this paper. Two traffic types are considered with different priorities. Two service policies are proposed to satisfy different performance requirements on cell loss probability and delay time of high priority traffic, respectively. A reflection method is employed to derive the probability that a cell successfully leaves the input buffer, then we obtain performance measures such as delay and cell loss probability. It is found that the performance is improved by adopting the multi-plane structure, and the two service policies are capable of guaranteeing the required quality of services

Published in:

Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on  (Volume:1 )

Date of Conference:

18-22 Jun 1995