By Topic

Use of exclusive-OR gates for boolean minimisation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Miessler, M.H. ; IBM UK Laboratories Ltd., Processor Systems Department, Winchester, UK

An algorithm for the minimisation of logic functions using XOR (exclusive-OR) gates in addition to AND, OR and INVERT gates is presented. It applies to functions with inherent symmetries, and the saving of hardware compared with that achieved by other minimisation methods is typically 40¿60%. The algorithm could be included in the minimisation part of an automated-logic design program, or used as a logic designer's tool, either in the form of an on-call program or in the form of two templates for quick manual application.

Published in:

Electrical Engineers, Proceedings of the Institution of  (Volume:119 ,  Issue: 9 )