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An algorithm for the minimisation of logic functions using XOR (exclusive-OR) gates in addition to AND, OR and INVERT gates is presented. It applies to functions with inherent symmetries, and the saving of hardware compared with that achieved by other minimisation methods is typically 40Â¿60%. The algorithm could be included in the minimisation part of an automated-logic design program, or used as a logic designer's tool, either in the form of an on-call program or in the form of two templates for quick manual application.
Electrical Engineers, Proceedings of the Institution of (Volume:119 , Issue: 9 )
Date of Publication: September 1972