Referenced Items are not available for this document.
An algorithm for the minimisation of logic functions using XOR (exclusive-OR) gates in addition to AND, OR and INVERT gates is presented. It applies to functions with inherent symmetries, and the saving of hardware compared with that achieved by other minimisation methods is typically 40¿60%. The algorithm could be included in the minimisation part of an automated-logic design program, or used as a logic designer's tool, either in the form of an on-call program or in the form of two templates for quick manual application.
Published in:
Electrical Engineers, Proceedings of the Institution of
(Volume:119
,
Issue:
9
)
Date of Publication: September 1972
- Page(s):
- 1269 - 1272
- ISSN :
- 0020-3270
- Digital Object Identifier :
- 10.1049/piee.1972.0245
- Date of Current Version :
- 26 January 2010
- Issue Date :
- September 1972
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