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Gate fan-in restrictions in logic circuits can be met at the design level by controlling the size of the sums and products of the corresponding Boolean expressions. A single-step procedure for meeting gate fan-in restrictions by limiting the size of the Boolean sums and products while retaining gate minimality is described. The steps are chosen to allow both hand and computer execution.
Electrical Engineers, Proceedings of the Institution of (Volume:118 , Issue: 2 )
Date of Publication: February 1971