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Browse Journals & Magazines > Electrical Engineers, Proceed ...> Volume:118 Issue:2 Help

Fan-in restrictions in logic circuits

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2 Author(s)
Zissos, D. ; University of Calgary, Department of Mathematics, Statistics & Computing Science, Calgary, Canada ; Duncan, F.G.

Gate fan-in restrictions in logic circuits can be met at the design level by controlling the size of the sums and products of the corresponding Boolean expressions. A single-step procedure for meeting gate fan-in restrictions by limiting the size of the Boolean sums and products while retaining gate minimality is described. The steps are chosen to allow both hand and computer execution.

Published in:
Electrical Engineers, Proceedings of the Institution of  (Volume:118 ,  Issue: 2 )

Date of Publication: February 1971

Page(s):
321 - 327
ISSN :
0020-3270
Digital Object Identifier :
10.1049/piee.1971.0057
Product Type:
Journals & Magazines
Date of Current Version :
26 January 2010
Issue Date :
February 1971

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