Referenced Items are not available for this document.
The source/load-pull design process of the input/output impedance matching network of a class E power amplifier is introduced in this paper. A design example of an LDMOS device MRF21010 at VHF band is given, and the results of the amplifier performance are simulated as a function of gate bias voltage, DC supply voltage, input power and frequency. The gain of 13.78 dB, the peak drain efficiency of 84.41%, and the power added efficiency of 80.08% are obtained whereupon the output power level is 38.78 dBm at 500 MHz.
Published in:
Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
Date of Conference: 23-25 July 2009
- Page(s):
- 742 - 745
- E-ISBN :
- 978-1-4244-4888-3
- Print ISBN:
- 978-1-4244-4886-9
- INSPEC Accession Number:
- 10879022
- Conference Location :
- Milpitas, CA
- Digital Object Identifier :
- 10.1109/ICCCAS.2009.5250395
- Product Type:
- Conference Publications
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