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The source/load-pull design process of the input/output impedance matching network of a class E power amplifier is introduced in this paper. A design example of an LDMOS device MRF21010 at VHF band is given, and the results of the amplifier performance are simulated as a function of gate bias voltage, DC supply voltage, input power and frequency. The gain of 13.78 dB, the peak drain efficiency of 84.41%, and the power added efficiency of 80.08% are obtained whereupon the output power level is 38.78 dBm at 500 MHz.
Date of Conference: 23-25 July 2009