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System-level synthesis: From specification to transaction level models

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1 Author(s)
Gajski, D.D. ; Center for Embedded Comput. Syst., Univ. of California, Irvine, Irvine, CA, USA

With design complexities increasing daily, the multi-core community is entertaining the idea of increasing the level of abstraction to transaction-level modeling (TLM) and design. However, the proper definition, style or semantics of TLM is not clear. Nor is it clear how to synthesize or verify TLMs. In this paper, we will introduce several TLM models and define their semantics. This formalism will allow us to define design decisions and corresponding model transformations that can be used to transform one model into another. These transformations and refinements are the enabler for automatic synthesis and verification on TLM. We will also discuss the algorithms and flow for model transformation according to the OSI network layers and show how to build tools with inputs and outputs at transaction level. We will conclude with preliminary tools and results that promise a productivity gain of several orders of magnitude.

Published in:

Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on

Date of Conference:

23-25 July 2009