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Equivalence checking of high-level designs based on symbolic simulation

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4 Author(s)
Matsumoto, T. ; VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan ; Nishihara, T. ; Kojima, Y. ; Fujita, M.

In this paper, we present a formal equivalence checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the equivalence faster when the similarity between the designs is large. We also show case studies of equivalence checking that were carried out with our verification framework FLEC.

Published in:

Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on

Date of Conference:

23-25 July 2009