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Rule-based equivalence checking of system-level design descriptions

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2 Author(s)
Yoshida, H. ; VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan ; Fujita, M.

This paper presents our study on rule-based equivalence checking of system-level design descriptions. The rule-based equivalence checking proves the equivalence of two system-level design descriptions by applying equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative equivalence rules. Since our equivalence checking method is based on potential internal equivalences identified by using random simulation, we also present how to prove the equivalence based on such potential internal equivalences. Finally, we explain our implementation of the rule-based equivalence checker and demonstrate its feasibility and efficiency using an example design.

Published in:

Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on

Date of Conference:

23-25 July 2009

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