Cart (Loading....) | Create Account
Close category search window
 

Synchronizing processors through memory requests in a tightly coupled multiprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Seznec, A. ; IRISA/INRIA, Rennes, France ; Jegou, Y.

The Greedy network, an interconnection network (IN) for tightly coupled multiprocessors (TCMs), is introduced. An original and cost-effective hardware mechanism is proposed. When DSPA pipeline processors are connected with a shared memory through a Greedy network and synchronized by the authors' synchronization mechanism, a very high parallelism may be achieved at execution time on a very large spectrum of loops, including loops where independency of the successive insertions cannot be checked at compile time

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.