A knowledge-based approach for worst-case timing analysis of microprocessor systems

A diagnostic system for microprocessor systems is being designed and developed. In microprocessor system diagnosis, temporal reasoning of event changes occurring at imprecisely known time instants is an important issue. The concept of time range has been proposed to capture the notion of time imprecision in event occurrence. According to this concept, efficient temporal reasoning techniques for time referencing, constraint satisfaction and propagation of time ranges have been developed for embedding domain knowledge in a deep level constraint model. The imprecision in these event contributes to a certain degree of uncertainty in the correctness of a microprocessor system operation. The proposed system performs worst case timing analysis. In particular, for the asynchronous bus operation of the MC68000 microprocessor, the sequence of events during a read cycle is traced through an inference process to determine if any constraint in the model is violated. Satisfactory results have been obtained in a practical implementation of the system using the CLIPS expert system shell