Closed-Form Delay and Crosstalk Models for $RLC$ On-Chip Interconnects Using a Matrix Rational Approximation

In this paper, a closed-form matrix rational-approximation algorithm is proposed to efficiently model the delay and crosstalk noise of coupled RLC on-chip interconnects. A key feature of the proposed algorithm is that, for any rational order, the approximation is obtained analytically in terms of predetermined coefficients and the per-unit-length parameters. As a result, the proposed method is not limited to fixed number of poles and provides a mechanism to increase the accuracy for cases when inductive effects are significant, the length of the line increases, or when the rise time of the signal becomes sharper. An error criterion is provided to select the order of approximation. The algorithm is tested for various single- and coupled-interconnect scenarios. The 50% delay and overshoot results match that of SPICE with less than 2% average error. The crosstalk results also accurately match those of SPICE with less than 4% average error.