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Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)

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3 Author(s)
Sung-Boem Park ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Ted Hong ; Subhasish Mitra

Instruction Footprint Recording and Analysis (IFRA) overcomes challenges associated with an expensive step in post-silicon validation of processors-pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-chip recorders collect instruction footprints (information about flows of instructions and what the instructions did as they passed through various design blocks) during the normal operation of the processor in a post-silicon system validation setup. Upon system failure, the recorded information is scanned out and analyzed offline for bug localization. Special self-consistency-based program analysis techniques, together with the test program binary of the application executed during post-silicon validation, are used for this purpose. Major benefits of using IFRA over traditional techniques for post-silicon bug localization are as follows: 1) it does not require full system-level reproduction of bugs, and 2) it does not require full system-level simulation. Simulation results on a complex superscalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:28 ,  Issue: 10 )