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Design and VLSI implementation of MPEG audio decoder

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3 Author(s)
Tsung-Han Tsai ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Thou-Ho Chen ; Liang-Gee Chen

The paper presents a chip design for an MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced to half of the original number, and the storage demand reduced too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words of memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using a silicon compiler structure in the Genesil system, with 0.8-μm CMOS technology

Published in:

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Date of Conference:

31 May-2 Jun 1995