Design and implementation of a 525 mm/sup 2/ CMOS digital micromirror device (DMD) display chip

This paper describes a new type of 1280/spl times/1024 Digital Micromirror Device (DMD) with 50 MHz serial I/O ports. The DMD uses a unique shadow memory and pixel multiplexing scheme to realize a high-definition television (HDTV) single-chip integrated circuit display device. The project developed defect-tolerant techniques based on memory cell duplication with address decoding to improve the fabrication yield of large-chip-size devices. This DMD chip is fabricated using 0.8 /spl mu/m single polysilicon and six-level metal CMOS process technology. A unique and optimized pixel with a pixel pitch of 17 /spl mu/m is obtained as a result of the 25/spl times/21 mm/sup 2/ compact chip design.