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A comprehensive study of the phosphorus dosage and annealing condition dependencies of boron-penetration and poly-depletion is presented. The experimental results show that the boron-penetration in BF/sub 2/ implanted poly-gate is significantly reduced as the dose of co-implanted phosphorus increases. The phosphorus dose of about 1.5/spl times/10/sup 15/ cm/sup -2/ in p/sup +/-poly gate can effectively retard the penetration of boron in BF/sub 2/3 to 5/spl times/10/sup 15/ cm/sup -2/ doped poly gate under 900/spl deg/C, 60 min annealing (30 min renew anneal, and 30 min post-contact implant anneal). The performance of boron-penetration-free phosphorus co-implanted p/sup +/-poly gate MOSFETs is also shown to be much better than the device with boron-penetration. In arsenic co-implanted p-poly gate, it also appears that arsenic co-implant would also retard boron penetrating through thin gate oxide. An optimal and effective gate processing for preventing boron-penetration is proposed for dual-gate CMOS devices.