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Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

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1 Author(s)
Shenai, K. ; Gen. Electr. Corp., Schenectady, NY, USA

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies

Published in:

Electron Devices, IEEE Transactions on  (Volume:37 ,  Issue: 4 )

Date of Publication:

Apr 1990

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