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A serial decimal adder is described which accepts numbers in binary-coded form. The binary digits, which are handled in parallel, are decoded into a set of pulses which actuate a built-in addition table storing all the possible sums. A special form of number representation has enabled the adder to be constructed more economically than would otherwise have been the case, while the advantages of this type of adder have been retained. The circuits use square-loop magnetic cores for all logical functions and junction transistors as pulse amplifiers.