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Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects

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6 Author(s)
Artundo, I. ; Dept. of Appl. Phys. & Photonics, Vrije Univ. Brussel, Brussels, Belgium ; Heirman, W. ; Loperena, M. ; Debaes, C.
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Photonic networks-on-chip have emerged as a viable solution for interconnecting multicore computer architectures in a power-efficient manner. Current architectures focus on large messages, however, which are not compatible with the coherence traffic found on chip multiprocessor networks. In this paper, we introduce a reconfigurable optical interconnect in which the topology is adapted automatically to the evolving traffic situation. This allows a large fraction of the (short) coherence messages to use the optical links, making our technique a better match for CMP networks when compared to existing solutions. We also evaluate the performance and power efficiency of our architecture using an assumed physical implementation based on ultra-low power optical switching devices and under realistic traffic load conditions.

Published in:

High Performance Interconnects, 2009. HOTI 2009. 17th IEEE Symposium on

Date of Conference:

25-27 Aug. 2009

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