By Topic

Use of symbolic analysis in analog circuit synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
G. Gieleu ; Katholieke Univ., Leuven, Belgium ; G. Debyser ; P. Wambacq ; I. Swings
more authors

A flexible and efficient program for the optimal sizing of analog integrated circuits is presented. The circuits are modeled with symbolic equations that are derived automatically by a symbolic simulator. The advantages and limitations of symbolic analysis for this application are investigated. Before optimization, the equations are ordered symbolically and then compiled in a way as minimize the overall evaluation time. The optimization tool then determines all device sizes and biasing for the circuit to meet the specifications while minimizing a user-defined cost function. Experimental results on realistic analog circuits show the efficiency of the approach

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:3 )

Date of Conference:

30 Apr-3 May 1995