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This paper presents a novel approach in the tuning of phase-locked loops (PLLs) for power electronic converters. PLLs are implemented inside a higher level controller to estimate the grid-voltage phase angle and then control the energy transfer between the power converter and the AC mains. The tuning of the PLL is not a trivial task, particularly when considering power-quality phenomena. In a general way, PLLs with a low bandwidth (low-gain PLLs) are required when handling distorted voltages. It is analytically demonstrated in this paper that low-gain PLLs have more tradeoffs than high-gain PLLs (e.g., PLLs for communications); it is not possible to optimize the settling time for a phase jump without making slower the PLL response to frequency variations. Existing tuning methods do not take into account low-gain features, which may result in nonoptimum designs. The proposed PLL tuning methodology is based on inspection of frequency-domain diagrams and, contrary to the other existing tuning methods, takes into account ldquolow-gainrdquo dynamics. It assures an optimized performance in the presence of any kind of disturbances in the grid. From a practical point of view, the proposed tuning procedure is very intuitive for controller designs. Some significant design examples and experimental results, obtained from a discrete implementation (dSpace platform), are provided in order to validate the theoretical approaches.