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An efficient implementation of 1-D median filter

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2 Author(s)
Moshnyaga, V.G. ; Dept. of Electron. Eng. & Comput. Sci., Fukuoka Univ., Fukuoka, Japan ; Hashimoto, K.

This paper presents a new architecture and circuit implementation of 1-D median filter. The proposed circuit belongs to the class of non-recursive sorting network architectures that process the input samples sequentially in the word-based manner. In comparison to the related schemes, it maintains sorting of samples from the previous position of the sliding window, positioning only the incoming sample to the correct rank. Unlike existing 1-D filter implementations, the circuit has linear hardware complexity, minimal latency and achieves throughput of 1/2 of the sampling rate. Experimental evaluation and comparisons show high efficiency of our design.

Published in:

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Date of Conference:

2-5 Aug. 2009