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A novel all-digital phase-locked loop with ultra fast frequency and phase acquisition

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2 Author(s)
Jun Zhao ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Yong-Bin Kim

An all-digital phase-locked loop (ADPLL) with fast acquisition and low power digitally controlled oscillator (DCO) is presented. The proposed ADPLL is designed with a unique lock-in process by employing a time-to-digital converter. Both the frequency of the reference clock and the delay between DCO output and DCO clock are measured. A carefully designed reset process reduces the phase lock into two cycles. The ADPLL was implemented using a 0.9 V 32 nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter < 67ps.

Published in:

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Date of Conference:

2-5 Aug. 2009