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An all-digital phase-locked loop (ADPLL) with fast acquisition and low power digitally controlled oscillator (DCO) is presented. The proposed ADPLL is designed with a unique lock-in process by employing a time-to-digital converter. Both the frequency of the reference clock and the delay between DCO output and DCO clock are measured. A carefully designed reset process reduces the phase lock into two cycles. The ADPLL was implemented using a 0.9 V 32 nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter < 67ps.