By Topic

Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Osaki, Y. ; Grad. Sch. of Electr. & Electron. Eng., Kobe Univ., Kobe, Japan ; Hirose, T. ; Matsumoto, K. ; Kuroki, N.
more authors

In this paper, we propose delay-compensation techniques for subthreshold digital circuits. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. To mitigate such variations, threshold-voltage monitoring and supply-voltage scaling techniques are adopted. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%.

Published in:

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Date of Conference:

2-5 Aug. 2009