Logic fault test simulation environment for IP core-based digital systems

A logic fault test simulation environment for core-based digital systems is proposed in this paper. The simulation environment emulates a typical built-in self-test (BIST) environment with test pattern generator that sends its outputs to a circuit under test (CUT) and the output streams from the CUT are fed into a response data analyzer. The developed simulator is suitable for testing digital IP cores. The paper describes in details the test architecture and application of the logic fault simulator. Some partial simulation results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided.