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Low power implementation of DCT for on-board satellite image processing systems

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2 Author(s)
Vijay, S. ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; Anchit, D.

Full adders are the significant elements which need to be analyzed for low-complexity implementation. Algorithms which minimize the complexity of multiplications of the input image matrix and the DCT matrix focus on reducing the number of full adders (NFAs) needed to implement the multiplication. In this paper, we have successfully proposed a novel technique to reduce considerably the NFAs, and thereby both the power consumption and time delay involved in implementing the image-DCT multiplication. The authors make use of row-column transformations of the input image matrix exploiting the symmetry of the DCT. Design results show that our method gives an average reduction in power of about 10.5% when compared to differential pixel implementation (DPI) and 16.5% when compared to the conventional implementation. The proposed method can also be made recursive, which can further reduce the NFAs for the implementation.

Published in:

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Date of Conference:

2-5 Aug. 2009

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