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A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer

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13 Author(s)
Xiaorong Luo ; State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Tianfei Lei ; Yuangang Wang ; Huanmei Gao
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Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/mum in the conventional devices on p-SOI layer to 27 V/mum, resulting in enhancement of the BOX electric field EI from 30 to 82 V/mum. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 10 )

Date of Publication:

Oct. 2009

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