A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer

Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 $ \hbox{V}/\mu\hbox{m}$ in the conventional devices on p-SOI layer to 27 $\hbox{V}/\mu\hbox{m}$, resulting in enhancement of the BOX electric field $E_{I}$ from 30 to 82 $ \hbox{V}/\mu\hbox{m}$. Moreover, holes located between the depleted n-islands help to increase $E_{I}$ as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.