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Prevention of Copper Interconnection Failure in System on Chip Using Virtual Metrology

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2 Author(s)
Imai, Shin-ichi ; Panasonic Corp., Moriguchi, Japan ; Kitabata, Masaki

This paper describes copper interconnection failure in a damascene process of a system on chip (SoC) caused by plating bath degradation in copper electroplating equipment. The physical analysis using cross-sectional transmission electron microscopy revealed the failure was caused by a void in a via-hole. By using equipment engineering system (EES) data of many variables in the equipment and some statistical methods, we clarified that the root cause in the interconnection failure is plating bath degradation, which denotes the increase in a byproduct, whose existence is confirmed by analyzing the plating bath using high-performance liquid chromatography (HPLC). More detailed HPLC analysis reveals that the byproduct, which is generated by decomposing a suppressor that is one of the additives, has lighter molecule weight than that of the suppressor. Therefore, the byproduct generated by the degradation in the plating bath causes void formation in a via-hole and causes interconnection failure. We also developed a virtual metrology (VM) model for the bath plating degradation due to the byproduct generation using a mathematical model. By performing VM fault detection and classification with the mathematical model, the interconnection failure was completely prevented without the increase in the manufacturing cost due to additional inspection.

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:22 ,  Issue: 4 )