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In semiconductor manufacturing, metrology of critical dimension (CD) is to ensure the quality of complicated processing steps and thus the quality of the fabricated chips by discovering faults or improvement opportunities. CD metrology has been considered the integrated part of the IC design and fabrication processes. Integrated Metrology (IM) is an enabler to achieve wafer-level control for technology nodes below 45 nm because of its capability of using the tool queue time to collect CD measurements and to avoid sampling lag to the control algorithms. How to maneuver the CD IM capability becomes a great challenge to the litho/etch processes. Focus of this research will be on the CD IM for the coater/developer track systems. We develop an IM sampling strategy with an optimum sampling plan to maximize the wafer-level control effectiveness subjected to the throughput, APC and SPC constraints. The optimum sampling problem is formulated and solved as an integer programming problem. Actual CD data are used to demonstrate and verify the proposed sampling methods.