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Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network

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8 Author(s)
Chih-Hao Liu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chien-Ching Lin ; Shau-Wei Yen ; Chih-Lung Chen
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A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 9 )

Date of Publication:

Sept. 2009

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