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Transistor scaling with the CMOS technology advancement results in f max saturation in contrast to fT improvement. Effective improvement methods for such saturated f max are presented to the transistors fabricated by 45- and 65-nm low standby power CMOS technology. The primary parameters investigated are V th optimization through adjusting the channel implantation and R sub control through adjusting the active to substrate contact spacing. It is demonstrated that V th optimization and R sub control result in more than 20% and 10% improvements for f max, respectively.