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An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 \mu m CMOS

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2 Author(s)
Seungsoo Kim ; Dept. of Radio Sci. & Eng., Kwangwoon Univ., Seoul, South Korea ; Hyunchol Shin

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.

Published in:

IEEE Microwave and Wireless Components Letters  (Volume:19 ,  Issue: 10 )