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Chip-level and board-level CDM ESD tests on IC products

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4 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Chih-Kuo Huang ; Yuan-Wen Hsiao ; Yong-Fen Hsieh

The electrostatic discharge (ESD) transient currents and failure analysis (FA) between chip-level and board-level charged-device-model (CDM) ESD tests are investigated in this work. The discharging current waveforms of three different printed circuit boards (PCBs) are characterized first. Then, the chip-level and board-level CDM ESD tests are performed to an ESD-protected dummy NMOS and a high-speed receiver front-end circuit, respectively. Scanning electron microscope (SEM) failure pictures show that the board-level CDM ESD test causes much severer failure than that caused by the chip-level CDM ESD test.

Published in:

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Date of Conference:

6-10 July 2009

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