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A novel dual pathway electrostatic discharge (ESD) protection device based on 0.6 mum CMOS p-well technology has been designed and fabricated according to the ISE-TCAD simulation tool and the C-R method. The new device was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new device has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.