By Topic

Design of a novel dual pathway ESD protection device using ISE-TCAD

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Zhang Bing ; School of Microelectronics, Xidian University, Key Laboratory of Ministry of Education for Wide Band-gap, Semiconductor Materials and Devices, Xi'an 710071, China ; Chai Changchun ; Ding Ruixue ; Xi Xiaowen

A novel dual pathway electrostatic discharge (ESD) protection device based on 0.6 mum CMOS p-well technology has been designed and fabricated according to the ISE-TCAD simulation tool and the C-R method. The new device was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new device has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.

Published in:

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

Date of Conference:

6-10 July 2009