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Design of a novel dual pathway ESD protection device using ISE-TCAD

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4 Author(s)
Zhang Bing ; Key Lab. of Minist. of Educ. for Wide Band-gap, Semicond. Mater. & Devices, Xidian Univ., Xi'an, China ; Chai Changchun ; Ding Ruixue ; Xi Xiaowen

A novel dual pathway electrostatic discharge (ESD) protection device based on 0.6 mum CMOS p-well technology has been designed and fabricated according to the ISE-TCAD simulation tool and the C-R method. The new device was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new device has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.

Published in:

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Date of Conference:

6-10 July 2009